1. Field of the Invention
The present invention relates to a semiconductor integrated circuit as a level conversion circuit comprising bipolar transistors and metal oxide semiconductor (MOS) transistors for converting positive complementary metal oxide semiconductor (CMOS) level signals to low current mode logic level (LCML) signals (it's range is from 0 V to 3 V, for example) or emitter coupled logic (ECL) level signals (it's range is from -0.9 V to -1.7 V, for example).
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing a configuration of a conventional level conversion circuit (or a level converter) for converting positive CMOS level signals to negative LCML level signals. In FIG. 1, the reference character VDD designates a voltage potential of a positive power source, VEE denotes a voltage potential of a negative power source, GND indicates a voltage potential of a ground power source. The reference character 1 designates an input terminal through which a positive CMOS voltage level (for example, a high (H) level is a voltage of a positive power source and a low level L is a voltage of the ground source) is inputted. The reference number 2 denotes an non-inverted output terminal through which a negative LCML level signal (for example, the H level is a ground voltage level and the L level is -0.3 V) is output to outside. The reference number 3 designates an non-inverted output terminal for outputting the LCML level signals. The reference number 6 denotes a supply terminal of a reference voltage VBB (for example, VBB is -1.3 V). The reference characters Q10, Q20, Q50, Q60 and Q70 designate NPN transistors (bipolar transistors), MN10 denotes a NMOS transistor, R10, R20, R70, and R80 indicate electrical resistance elements as load resistance elements, and Is and Is1 indicate constant power sources. The reference number 70 designates a CMOS-ECL conversion section for converting positive CMOS level signals output from a CMOS output circuit to negative ECL level signals, and 80 denotes a ECL-LCML conversion section for converting negative ECL level signals to negative LCML level signals.
FIG. 2 is a circuit diagram showing a configuration of another conventional level conversion circuit for converting positive CMOS level signals to negative ECL level signals. In FIG. 2, the reference character VDD designates a voltage potential of a positive power source and VEE denotes a voltage potential of a negative power source, and GND indicates a voltage potential of a ground power source. The reference number 1 designates an input terminal through which a positive CMOS level signal is inputted. The reference number 4 denotes an non-inverted output terminal through which a negative ECL level signal (for example, the H level is -0.9 V and the L level is -1.7 V) is output, 5 denotes an non-inverted output terminal through which a ECL level signal is output, and 6 indicates a supply terminal through which a reference voltage potential VBB (for example, VBB is -1.3 V) is supplied. The reference characters Q10, Q20, Q30, Q40, Q50, Q60, and Q70 designate NPN transistors, MN10 indicates a NMOS transistor, R30, R40, RS0, R60, R70, and R80 designate electrical resistance elements. The reference characters Is and Is1 denote constant current sources, 70 designates a CMOS-ECL conversion section for converting positive CMOS level signals output from the CMOS output circuit to negative ECL level signals, and 90 indicates an ECL circuit
Next, a description will now be given of the conventional level conversion circuit.
The following description will explain both cases in which a positive CMOS level signal to be inputted to the input terminal 1 has both levels, the H voltage potential level and the L voltage potential level. Because the MOS transistor MN10 becomes ON when the positive CMOS level to be inputted into the input terminal 1 is the H level, a voltage potential of the emitter terminal of the NPN transistor Q60 is reduced by the voltage potential VBB (a forward voltage between a base and an emitter is approximately 0.8 V) from the ground voltage potential. A voltage potential of the emitter terminal of the NPN transistor Q70 as an input of the ECL-LCML conversion section 80 is reduced by the voltage potential VBE (-2.0 V) from the ground potential. This voltage potential of the emitter terminal of the NPN transistor Q70 is lower than the reference voltage potential VBB, the current Is flows through the NPN transistor Q20. Thereby, the voltage potential of the non-inverted output terminal 2 becomes the H level (as the level of the ground voltage potential) and the voltage potential of the LCML non-inverted output terminal 3 becomes the L level (for example, -0.3 V) because a voltage drop determined by the magnitude of the current Is and the value of the load resistance R20 occurs.
Furthermore, because the MOS transistor MN10 becomes ON when the positive CMOS level to be inputted into the input terminal 1 is the L level, the current flows from the power source VDD through the NPN transistor Q50 as a diode and the voltage potential of the base terminal of the NPN transistor Q60 becomes VBE. Accordingly, the voltage potential of the emitter terminal of the NPN transistor Q70 becomes -VBE. Because the voltage potential of the emitter terminal of the NPN transistor Q70 is higher than the reference voltage potential VBB, the constant current Is flows through the NPN transistor Q10. Accordingly, the voltage potential of the non-inverted output terminal 2 of the LCML level becomes the L level, and the voltage potential of the non-inverted output terminal 3 of the LCML level becomes the H level.
Because the principle of operation of the conventional level conversion circuit shown in FIG. 2 is the same as that of the conventional level converter shown in FIG. 1, the explanation of the principle of operation will be omitted here. Specifically, when both the conventional level conversion circuits shown in FIGS. 1 and 2, the magnitude of a voltage drop in the conventional conversion circuit shown in FIG. 2, that is determined by the magnitude of the constant current Is and the magnitude of the load resistances R50 and R60, becomes larger (for example, it becomes 0.8 V) than that of the conventional level conversion circuit shown in FIG. 1. It is therefore required for the conventional conversion circuit shown in FIG. 2 to further incorporate an emitter follower output circuit for level shift operation.
The voltage potential of each of the non-inverted output terminals 4 and 5 as the ECL output terminal becomes -0.9 V in the H level and -1.7 V in the L level.
Because the conventional level conversion circuits as semiconductor integrated circuits have the above configurations and the positive CMOS voltage level is converted into ECL voltage level before the negative LCML voltage level or the negative ECL voltage level, it is required to incorporate an extra gate, for example, it comprising the NPN transistors Q60, Q70, the constant current source Is1, and the load resistance R80. This conventional configuration of the level conversion circuit causes the increasing of both the delay time of operation and the power consumption, and it is also difficult to increase the degree of the integration of the level conversion circuit as a semiconductor integrated circuit.